The present invention relates to amplifiers. More particularly, the present invention relates to a low voltage amplifier.
The demand for improved operational amplifiers, and in particular low power, operational amplifier circuits for high-precision data acquisition and instrumentation applications, such as multi-channel data acquisition systems, audio processing, test equipment and other consumer electronics applications continues to increase. Such operational amplifier circuits generally include an input stage circuit and an output stage circuit comprised of various amplifier devices and other current sources.
The input stage of many operational amplifier circuits, for example one comprising a differential pair arrangement of transistors, is configured for sensing a differential input voltage, which may realize inherent errors with offset voltage, bias current, offset voltage drift, and noise. The design of the input stage is typically aimed at minimizing these errors, while maintaining low current consumption, and with a large portion of the rail-to-rail input range being made available for common-mode signals.
Output stages are generally configured to provide a load impedance ZL with a desired output voltage VOUT and current IOUT, resulting in an output power POUT=VOUTIOUT. The typical main requirements of output stages are to provide negative and positive output currents at high current efficiency, an output voltage range that efficiently uses the full rail-to-rail range, i.e., from the negative supply rail to the positive supply rail, low distortion, and good high-frequency performance.
Class-AB biasing is often used to improve performance of output stage devices due to the ability to eliminate cross-over distortion by biasing the output transistors at a small, but finite, current Class-AB biasing is similar to class-A biasing in that the output transistors are maintained xe2x80x9conxe2x80x9d, and similar to class-B biasing in that the output transistors are biased at a much smaller current than the peak current delivered to the load. Class-AB biasing can be configured with feedforward biasing or with feedback biasing. Feedforward biasing is utilized when the biasing is fixed by components in series or in parallel with the signal path, while in feedback biasing uses a feedback loop to provide the class-AB biasing.
With reference to FIG. 1, an operational amplifier circuit 100 comprising an input stage 102 and an output stage 104 is illustrated as separate stages, which can be directly connected, or coupled through other stages. Such a class-AB configuration is often referred to as direct class-AB biasing.
Input stage 102 comprises a differential pair of transistors M1 and M2. The difference in input current from a source I1, at the sources of transistors M1 and M2 is derived at the drains as signal currents, SIGNAL1, and SIGNAL2. Difference currents SIGNAL1, and SIGNAL2 can be fed into multiple stage applications with appropriate level shifting, e.g., folded cascode or other stage applications, such as output stage 104.
Output stage 104 comprises a class-AB biasing configuration including biasing transistors B1-B4, a pair of complementary signal devices M3 and M4, and a pair of output devices, M5 and M6. Output stage 104 is configured to source current in output device M5 and to sink current through output device M6. It is desirable for output stage 104 to be able to fully swing from the positive rail to the negative rail, i.e., from VS+ to ground. This generally requires output devices M5 and M6 to be driven as common source devices. As common source devices, it is difficult to provide biasing when no current is flowing through output devices M5 and M6. Further, when there is little or no output current at zero load, output devices M5 and M6 must still maintain a low dynamic output impedance. Without class-AB biasing, the output current could not go to zero, or the output impedance would be extremely high. However, the class-AB biasing configuration facilitates zero current under a zero load condition.
For example, biasing transistors B1 and B2 are connected in series and configured with a controlled current source I2 to supply two gate-source voltages VGS to the gate of transistor M3. Transistor M3 comprises a source follower that supplies current to the gate of transistor M5, thus providing a first, upper controlled VGS loop, with the gate-source voltages VGS of biasing transistors B1 and B2 equaling the gate-source voltages VGS of transistors M3 and M5. The current flow within the upper VGS loop is defined by the areas and current flow within the devices. A current source I4 is configured to provide a controlled current through transistor M3. Thus with controlled current provided through biasing transistors B1 and B2 and transistor M3, the current flow in transistor M5 can be substantially controlled. Similarly, a second, lower controlled VGS loop is provided with biasing transistors B3 and B4, transistor M4, and a controlled current source I5 to control the nominal current flow in transistor M6.
During operation, when transistor M5 sources (or supplies) more current, the gate-source voltage VGS of transistor M5 increases; since the gate of transistor M3 is constant, the gate-source voltage VGS of transistor M3 must decrease, resulting in less current flow through transistor M3. Therefore, some of the current supplied to a node 106 must be diverted instead to transistor M4, resulting in the gate-source voltage VGS of transistor M4 getting larger, thus decreasing or cutting off the gate-source voltage VGS of transistor M6, i.e., as transistor M5 sources more current, transistor M6 is cut off. Conversely, as transistor M6 sinks (or requires) more current, transistor M5 is cut off. For no load current, half of the current into node 106 flows through transistor M3 and the other half through the drain of transistor M4 to supply bottom current source 15, resulting in nominal biasing of output devices M5 and M6, i.e., a quiescent current condition with zero load current.
Unfortunately, for the upper and lower loops of output stage 104 to effectively bias the gates of transistors M3 and M4 at least two gate-source voltage VGS are needed. For typical CMOS processes, this two gate-source voltage VGS condition requires at least two volts or more, which is significantly higher than the low voltage operation, e.g., 1.8 volt or less, that is being demanded in current applications.
In accordance with various aspects of the present invention, an operational amplifier is configured for low voltage operation and better compliance. In accordance with an exemplary embodiment, an operational amplifier comprises a folded-cascode amplifier with a class-AB biased output stage configured for low voltage operation. The exemplary output stage includes a class-AB control loop being controlled for the upper output device, and with the complementary, lower output device being configured with an additional gain arrangement to allow for the necessary compliance voltage. The lower output device is configured to operate with a low gate-source voltage without significantly affecting the load impedance seen by a difference current received from an input stage. This configuration significantly increases the gain of the operational amplifier.
In accordance with an exemplary embodiment, the upper devices of the output stage can be configured with a cascoded mirror and a class-AB control loop driven by a charge pump to meet and/or exceed compliance voltage requirements for the upper devices.